Prior art NMOS and even some CMOS integrated circuits are equipped with means for applying a negative voltage, V.sub.BB, to the substrate with respect to the ground node, V.sub.SS. Several beneficial effects are realized from that practice:
First, junction capacitances are greatly reduced since the N+/P junctions have a minimum reverse bias equal to the back bias V.sub.BB. Since the capacitance/voltage characteristic of a junction diode is inherently a square root function, the first few volts of reverse bias has the largest effect on reduction of the junction capacitance.
Second, threshold voltages are effected by the back bias with the largest effect again being seen during the first two volts of back bias (See FIG. 1) because of the aforementioned square root capacitance/voltage relationship and also because of the fact that the surface doping is heavier than the substrate doping.
Third, other transistor characteristics, such as punch through resistance, are also improved by increasing back bias.
In the interest of conserving chip terminal connections, negative back bias is generally provided on-chip rather than being applied from off-chip.
A typical prior art on-chip back bias generator is shown in schematic form in FIG. 2. It comprises a one stage capacitive charge pump. An on-chip ring oscillator having a frequency of between five and twenty megahertz (not shown) is used to drive node 10 through push-pull buffer 12, 14, 16. One deficiency of the device is illustrated by the fact that it does not provide a voltage swing fully equal to V.sub.CC -V.sub.SS. Transistor 14 is typically an enhancement mode transistor which causes a voltage drop of V.sub.T14. During the positive swing of node 10 (see FIG. 3 at reference numeral 11), node 24 is clamped by the enhancement type transistor 28 to a voltage of +V.sub.T28 above V.sub.SS. Thus capacitor 30, a depletion mode transistor with source and drain shorted together, is charged with its positive terminal (connected to node 10) equal to a value of +(V.sub.cc -V.sub.T14) volts and with its negative terminal (connected to node 24) equal to a value of +V.sub.T28, the forward drop through transistor 28. During the negative swing of node 10 (see FIG. 3, reference numeral 20), the positive capacitor terminal (connected to node 10), previously at +(V.sub.CC -V.sub.T14) is pulled to zero volts and, thus, the negative capacitor 30 terminal goes to a voltage equal to -(V.sub.CC -V.sub.T14 -V.sub.T28), if there is no charge transfer through transistor 34.
If V.sub.BB is less negative than -(V.sub.CC -V.sub.T14 -V.sub.T28 -V.sub.T34), there will be a charge transfer and V.sub.BB is pulled negative through the diode connected enhancement transistor 34 until V.sub.BB reaches the above specified voltage, -(V.sub.CC -V.sub.T14 -V.sub.T28 -V.sub.T34). For back bias generators in the prior art having charge storage nodes, a potentially harmful side effect is that parasitic diode (shown in FIG. 4) could be turned on. Any diode current will inject electrons into the substrate, which, due to long minority carrier lifetime, could diffuse to the charge storage nodes and discharge those nodes. Parasitic diode 36 is in parallel with diode connected enhancement transistor 34 and thus this translates to the requirement that the gate-to-source=drain-to-source voltage drop, V.sub.T34 (at V.sub.BS =+V.sub.T34), where V.sub.BS is the Bulk to Source (back bias voltage) between substrate and source of transistor 34, must be less than the forward voltage, V.sub.F, of N+/P diode 36.
The current/voltage characteristic of the N+/P diode is logarithmic: EQU V.sub.F =(k*T/q)*ln(I/I.sub.s)
with I.sub.s being the saturation current at zero bias (which is proportional to the diode area). The current/voltage characteristic of transistor 34 "diode" is a square law function EQU V.sub.GS .about.square root of I.sub.DS
It is clear, then, that the requirement that V.sub.F must be smaller than V.sub.GS is a matter of absolute current tolerance.
In order to minimize electron injection by forward current through diode 36, FIG. 4, it is necessary to minimize forward voltage across diode 36 (VF) and/or minimize the area (size) of diode 36.
Beside the above mentioned voltage deficiencies which reduce maximum back bias voltage output, the circuit shown in FIG. 2 also has some current deficiencies. For a high output voltage, it is desirable to have the threshold voltage of transistors 28 and 34 as low as possible. In addition, the threshold voltage of transistor 34 should be low in order to prevent the junction diode from turning on. During second phase 32 (see FIG. 3) transistor 28 is supposed to be turned off, otherwise the charge of capacitor 30 would leak to V.sub.SS rather than being transferred to V.sub.BB. But during second phase 32, the back bias of transistor 28 is positive with a value of V.sub.T34. This positive back bias lowers the threshold voltage to such a degree that transistor 28 may turn on partially. To prevent that, the back bias for transistor 28 must be increased by reducing V.sub.T34.
But during phase one 26 (see FIG. 3), transistor 34 may then leak. (FIG. 3 also illustrates the excursions of node 24, see reference numeral 13.) The following relationship holds: EQU V.sub.BB (max)=[V.sub.CC -V.sub.T14 (at V.sub.BS .apprxeq.4.0 v+.vertline.V.sub.BB .vertline.)-V.sub.T28 (at V.sub.BS =V.sub.BB)-V.sub.T34 (at V.sub.BS =-V.sub.T14)]
The dilemma of contradicting requirements is illustrated in the drawings of FIG. 5a, 5b and 5c. It is also necessary to consider that transistor 34 usually is quite large in order to minimize the forward voltage drop, but this usually translates to a requirement for a large diode area. FIG. 5a addresses transistor 28 during phase two 32 (see FIG. 3) and shows that:
V.sub.24 .apprxeq.-3.5 volts, and PA1 V.sub.BB .apprxeq.-3.0 volts PA1 V.sub.DS .apprxeq.+3.5 volts (large S/D voltage) PA1 V.sub.SB +0.5 volts (positive `back` bias) PA1 I.sub.DS =minimum leakage under above adverse conditions PA1 V.sub.24 .apprxeq.-3.5 volts, and PA1 V.sub.SB =V.sub.DS .apprxeq.0.2 volts=V.sub.T34 PA1 I.sub.DX =negligible (current through parasitic diode DX) which requires V.sub.T34 to be high. PA1 V.sub.24 =V.sub.T28 .apprxeq.0.7 volts, and PA1 V.sub.BB =-3.0 volts PA1 V.sub.DS .apprxeq.+3.7 volts (high source drain voltage) PA1 V.sub.SB =0 volts (zero back bias) PA1 I.sub.DS =minimum leakage (under above adverse conditions) PA1 V.sub.GS =5.0 volts PA1 V.sub.DS =0 volts PA1 V.sub.G =-V.sub.T31 volts PA1 V.sub.S .apprxeq.-3.5 volts PA1 V.sub.GS .apprxeq.(3.5-V.sub.T31).apprxeq.+3.0 volts PA1 V.sub.SB =+0.2 volts
FIG. 5b addresses transistor 34 during phase two 32 (see FIG. 3) and shows that:
FIG. 5c addresses transistor 34 during phase one 26 (see FIG. 3) and shows that:
One prior art attempt at a solution set as a goal getting the full value of V.sub.CC as a charge across capacitor 30. Referring to FIG. 6, the positive terminal of capacitor 30 (connected to node 10) was charged fully to V.sub.CC by a bootstrap (not shown, but the circuit would be similar to that of FIG. 2, reference numeral 19) to pull up gate 15 of the push-pull driver 14, and the negative terminal of capacitor 30 (connected to node was clamped solidly to V.sub.SS by disconnecting the gate of transistor 28 from its drain and pulling it to V.sub.CC during phase one 26 (see FIG. 3). During phase two 32, the gate of transistor 28 is connected to the drain (node 24), but the pull-up of the gate cannot be disconnected and leaks large amounts of current from V.sub.CC to node 24. During phase one 26 (FIG. 3) transistor 34 must isolate V.sub.BB from node 24 which requires negligible leakage of transistor 34 with +0.2 V back bias, +0.2 V V.sub.GS and a drain source voltage of approximately (V.sub.BB +V.sub.T34)=4.0 volts. This would require a relative high threshold for transistor 34, but the high threshold voltage would cause a high positive (forward bias) back bias during phase two 32 (FIG. 3) for transistor 28.
During phase one 26, transistor 28 operating conditions are as follows:
During phase two 32, transistor 28 operating conditions are as follows:
Transistor 31 is not only leaking during phase two 32 (FIG. 3), but it is solidly turned on with V.sub.S =-V.sub.BB -V.sub.T34, V.sub.G =0 and V.sub.D =V.sub.CC, resulting in a V.sub.DS of approximately 9.0 volts, a V.sub.BS of approximately +0.2 volts and a V.sub.GS of approximately 3.2 volts. In the particular prior art circuit, the geometry of transistor 31 was 6 by 14 microns, not very small. The purpose of resistor 33 was to limit the peak current (C*dv/dt) through capacitor 30 which is also the peak current through the parallel combination of transistor 34 and the junction substrate diode (not shown) if it were not for the large leakage current from V.sub.CC. By limiting the current through transistor 34 (by limiting the current through transistor 16), the maximum V.sub.GS voltage drop is limited so that it (hopefully) does not exceed a V.sub.F of the junction diode.
This effort to improve the voltage deficiencies of the circuit by removing the voltage drop across the clamping diode 28 appears to have introduced such a gross current deficiency that circuit performance is probably worse than prior to the "improvements".